Integrated circuits (ICs) typically include a plurality of semiconductor devices and interconnect wiring. Networks of metal interconnect wiring are often used to connect the semiconductor devices from the semiconductor portion of the substrate. Multiple levels of metal interconnect wiring form a plurality of metallization layers above the semiconductor portion of the substrate and are connected together to form a back-end-of-the-line (“BEOL”) interconnect structure. Within such a structure, metal lines run parallel to the substrate in the metallization layers and conductive vias run perpendicular to the substrate between the metallization layers to interconnect the metal lines.
High performance of contemporary ICs may be achieved using a highly conductive metal, such as copper, as the interconnect metal of the BEOL interconnect structure, which also employs a low dielectric constant material or dielectric material as an interlevel dielectric (ILD) layer or layers. To help hold the highly conductive interconnect metal to the dielectric material, a metal liner material, such as tantalum or tantalum nitride, is deposited onto the dielectric material to form a metal liner layer. Then, a conductive metal seed layer, such as a layer of copper or copper alloy, is formed on the metal liner layer and the highly conductive metal is deposited over the conductive metal seed layer to form a metal interconnect wire.
During normal operation, the temperature of the IC will generally increase due to, for example, the relatively large power consumption by the semiconductor devices. This increased temperature can produce relatively high thermal stresses in the IC including in the BEOL interconnect structure due to the thermal expansion differences between the conductive metal(s) and the dielectric material(s) that form the interconnect structure. These relatively high thermal stresses can result in cracking and/or delamination (e.g., peeling) of or between the various metallization layers. To address this issue, one approach has been to fabricate crack-arresting or crack-stop structures that extend through the metallization layers perpendicular to the substrate. These crack-stop structures help hold the BEOL interconnect structure together as well as help prevent diffusion of moisture into the BEOL interconnect structure, which can further increase cracking and/or delamination of or between the metallization layers. Unfortunately, current crack-stop structures are not always effective at holding the BEOL interconnect structure together, and can fail or delamination themselves allowing cracking and/or delamination of or between the metallization layers.
Accordingly, it is desirable to provide integrated circuits having crack-stop structures with improved robustness to arrest cracking and/or delamination of or between metallization layers disposed above semiconductor substrates and methods for fabricating such integrated circuits. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.